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Contents |
5 |
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Preface |
10 |
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Acknowledgments |
20 |
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Introduction |
21 |
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Application areas and examples |
21 |
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Common characteristics |
24 |
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Challenges in Embedded System Design |
30 |
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Design Flows |
32 |
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Structure of this book |
37 |
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Assignments |
38 |
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Specifications and Modeling |
40 |
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Requirements |
40 |
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Models of computation |
47 |
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Early design phases |
54 |
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Use cases |
54 |
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(Message) Sequence Charts |
55 |
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Communicating finite state machines (CFSMs) |
58 |
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Timed automata |
59 |
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StateCharts: implicit shared memory communication |
61 |
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Synchronous languages |
71 |
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SDL: A case of message passing |
73 |
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Data flow |
80 |
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Scope |
80 |
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|
Kahn process networks |
81 |
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Synchronous data flow |
83 |
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Simulink |
85 |
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Petri nets |
86 |
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Introduction |
86 |
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Condition/event nets |
89 |
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Place/transition nets |
90 |
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Predicate/transition nets |
95 |
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Evaluation |
97 |
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Discrete event based languages |
97 |
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|
VHDL |
99 |
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SystemC |
115 |
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Verilog and SystemVerilog |
117 |
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SpecC |
119 |
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Von-Neumann languages |
120 |
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CSP |
121 |
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ADA |
121 |
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Java |
124 |
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|
Pearl and Chill |
125 |
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Communication libraries |
125 |
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Levels of hardware modeling |
126 |
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Comparison of models of computation |
128 |
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Criteria |
128 |
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UML |
132 |
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Ptolemy II |
134 |
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Assignments |
135 |
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Embedded System Hardware |
138 |
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Introduction |
138 |
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Input |
139 |
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Sensors |
139 |
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Discretization of time: Sample-and-hold circuits |
142 |
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Discretization of values: A/D-converters |
146 |
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Processing Units |
151 |
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Overview |
151 |
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Application-Specific Circuits (ASICs) |
154 |
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Processors |
154 |
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Reconfigurable Logic |
171 |
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Memories |
174 |
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Communication |
176 |
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|
Requirements |
177 |
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Electrical robustness |
178 |
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Guaranteeing real-time behavior |
179 |
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Examples |
181 |
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Output |
183 |
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D/A-converters |
183 |
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Sampling theorem |
186 |
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Actuators |
191 |
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Secure hardware |
192 |
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Assignments |
192 |
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System Software |
195 |
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Embedded Operating Systems |
196 |
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General requirements |
196 |
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Real-time operating systems |
200 |
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Virtual machines |
204 |
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Resource access protocols |
204 |
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ERIKA |
209 |
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Hardware abstraction layers |
213 |
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Middleware |
213 |
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OSEK/VDX COM |
213 |
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CORBA |
214 |
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MPI |
215 |
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POSIX Threads (Pthreads) |
216 |
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OpenMP |
216 |
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UPnP, DPWS and JXTA |
217 |
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Real-time databases |
218 |
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Assignments |
219 |
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Evaluation and Validation |
220 |
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Introduction |
220 |
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Scope |
220 |
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Multi-objective optimization |
221 |
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Relevant objectives |
223 |
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Performance evaluation |
224 |
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Early phases |
224 |
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WCET estimation |
225 |
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Real-time calculus |
230 |
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Energy and power models |
234 |
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Thermal models |
235 |
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Risk- and dependability analysis |
236 |
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Simulation |
245 |
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Rapid prototyping and emulation |
246 |
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Formal Verification |
248 |
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Assignments |
250 |
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Application mapping |
252 |
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Problem definition |
252 |
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Scheduling in real-time systems |
255 |
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Classification of scheduling algorithms |
255 |
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Aperiodic scheduling without precedence constraints |
259 |
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Aperiodic scheduling with precedence constraints |
265 |
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Periodic scheduling without precedence constraints |
274 |
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Periodic scheduling with precedence constraints |
279 |
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Sporadic events |
280 |
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Hardware/software partitioning |
280 |
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Introduction |
280 |
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COOL |
281 |
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Mapping to heterogeneous multi-processors |
289 |
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Assignments |
294 |
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Optimization |
297 |
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Task level concurrency management |
297 |
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High-level optimizations |
301 |
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Floating-point to fixed-point conversion |
301 |
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Simple loop transformations |
303 |
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Loop tiling/blocking |
305 |
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Loop splitting |
307 |
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Array folding |
309 |
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Compilers for embedded systems |
311 |
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Introduction |
311 |
|
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Energy-aware compilation |
312 |
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Memory-architecture aware compilation |
313 |
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Reconciling compilers and timing analysis |
322 |
|
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Compilation for digital signal processors |
324 |
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Compilation for multimedia processors |
326 |
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Compilation for VLIW processors |
327 |
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Compilation for network processors |
328 |
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Compiler generation, retargetable compilers and design space exploration |
329 |
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Power Management and Thermal Management |
329 |
|
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Dynamic voltage scaling (DVS) |
329 |
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Dynamic power management (DPM) |
333 |
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Assignments |
334 |
|
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Test |
337 |
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Scope |
337 |
|
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Test procedures |
338 |
|
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Test pattern generation for gate level models |
338 |
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Self-test programs |
340 |
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Evaluation of test pattern sets and system robustness |
340 |
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Fault coverage |
340 |
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Fault simulation |
341 |
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Fault injection |
342 |
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Design for testability |
343 |
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Motivation |
343 |
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Scan design |
343 |
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Signature analysis |
345 |
|
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Pseudo-random test pattern generation |
346 |
|
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The built-in logic block observer (BILBO) |
347 |
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Assignments |
348 |
|
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Integer linear programming |
350 |
|
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Kirchhoff's laws and operational amplifiers |
352 |
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References |
357 |
|
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About the Author |
386 |
|
|
List of Figures |
387 |
|
|
Index |
394 |
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