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Preface |
6 |
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Contents |
9 |
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1 Properties and Advantages of Gallium Nitride |
11 |
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1.1 General Background |
11 |
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1.2 GaN Material |
12 |
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1.3 Polarization Effect |
16 |
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1.4 GaN-Based FET |
19 |
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1.5 Natural Super Junction (NSJ) Structure |
21 |
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1.6 On-Resistance and Breakdown Voltage |
24 |
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1.7 Low-Voltage Devices |
25 |
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1.8 High-Voltage Devices |
29 |
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1.9 Future Study in GaN Vertical Power Device |
33 |
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References |
35 |
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2 Substrates and Materials |
37 |
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2.1 Substrate Overview |
38 |
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2.2 Metal-Organic Chemical Vapor Deposition |
40 |
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2.2.1 Fabrication of Semi-insulating (S.I.) (Al,Ga)N Layers |
42 |
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2.2.2 n- and p-Type Doping |
43 |
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2.2.3 AlGaN/GaN Heterostructures |
44 |
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2.3 Traps and Dispersion |
45 |
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2.4 Fabrication of Epitaxial Structures for Lateral Power Switching Devices |
45 |
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2.4.1 Current-Blocking Layer Deposition on Silicon Substrates |
47 |
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2.4.2 Current-Blocking Layer Deposition on Silicon Carbide Substrates |
48 |
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2.4.3 Current Blocking Layer Deposition on Sapphire Substrates |
48 |
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2.4.4 Gating Layer Growth |
50 |
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2.5 Vertical Devices |
50 |
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2.6 Outlook |
55 |
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2.6.1 InAlN and AlInGaN Barrier Layers |
55 |
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2.6.2 Devices Based on Non-c-plane GaN |
56 |
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References |
57 |
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3 GaN-on-Silicon CMOS-Compatible Process |
63 |
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3.1 GaN-on-Si Epitaxy |
63 |
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3.2 GaN-on-Si Au-Free Processing |
65 |
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3.3 Au-Free Ohmic Contact |
69 |
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3.3.1 AlGaN Barrier Recess |
71 |
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3.3.2 Ohmic Alloy Optimization |
71 |
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3.3.3 Ti/Al Ratio |
72 |
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3.3.4 Si Layer at Bottom of Ohmic Metal Stack |
73 |
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3.4 Gallium Contamination Issues |
74 |
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3.5 Conclusion |
77 |
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References |
77 |
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4 Lateral GaN Devices for Power Applications (from kHz to GHz) |
79 |
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4.1 Introduction |
79 |
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4.2 History of AlGaN/GaN HEMTs |
79 |
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4.3 Addressing Dispersion |
81 |
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4.4 Gallium Nitride for mm-Wave Applications |
84 |
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4.5 Historical Perspective of N-Polar GaN Development |
86 |
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4.6 GaN Applied to Power Electronics |
95 |
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4.7 Conclusions |
102 |
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Acknowledgments |
103 |
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References |
103 |
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5 Vertical Gallium Nitride Technology |
110 |
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5.1 Introduction |
110 |
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5.2 Device Topology |
112 |
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5.2.1 Vertical Devices Versus Lateral Devices |
112 |
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5.3 Evolution of a CAVET |
114 |
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5.4 Design of a CAVET |
117 |
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5.4.1 A Discussion of the Key Components Required for the Successful Functioning of the Device |
117 |
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5.5 The Key Components of a CAVET |
119 |
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5.5.1 Current Blocking Layers |
124 |
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5.5.2 Performance and Cost |
126 |
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5.6 Role of Bulk GaN Substrate |
127 |
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5.7 CAVETs for RF Application |
128 |
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5.8 Conclusion |
128 |
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Acknowledgments |
129 |
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References |
129 |
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6 GaN-Based Nanowire Transistors |
131 |
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6.1 Introduction |
131 |
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6.1.1 Bottom-Up Nanowire Devices: GaN Nanowire Field-Effect Transistors |
133 |
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6.1.2 Top-Down Nanowire Devices |
135 |
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6.1.2.1 Tri-Gate GaN Transistors for Power Electronics Applications |
135 |
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6.2 Tri-Gate GaN Power MISFET |
135 |
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6.2.1 Additional Considerations of Tri-gate GaN Power Transistors |
139 |
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6.3 Nanowires for RF Applications: Increasing Linearity of Gm |
142 |
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6.4 Nanostructured GaN Schottky Barrier Diodes |
145 |
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6.4.1 Nanostructured Anode for GaN SBDs |
145 |
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6.5 Conclusions |
148 |
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References |
150 |
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7 Deep-Level Characterization: Electrical and Optical Methods |
153 |
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7.1 Introduction |
153 |
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7.2 Fundamentals of DLTS and DLOS |
155 |
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7.2.1 C-DLTS |
155 |
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7.2.2 C-DLOS |
157 |
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7.2.3 Applicability of C-DLTS and C-DLOS to HEMTs |
158 |
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7.2.4 I-DLTS and I-DLOS |
159 |
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7.3 Application of DLTS and DLOS to GaN HEMTs |
161 |
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7.3.1 Using Fill Pulses to Spatially Locate Traps |
162 |
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7.3.2 Using Measurement Bias to Spatially Locate Traps |
166 |
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7.3.3 Additional Methods to Measure Spatially Localized Traps |
168 |
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7.4 Conclusion |
169 |
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References |
170 |
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8 Modelling of GaN HEMTs: From Device-Level Simulation to Virtual Prototyping |
172 |
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8.1 Introduction |
172 |
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8.2 Device-Level Simulation |
174 |
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8.2.1 Pulsed Mode Behavior |
177 |
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8.3 Non-optimized Buffer Technology |
177 |
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8.4 Optimized Buffer Technology |
181 |
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8.4.1 AC Capacitances |
183 |
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8.4.2 Off-state Breakdown |
185 |
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8.5 Spice Model Development and Calibration |
187 |
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8.6 Application Board Characterization and Simulations |
189 |
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8.6.1 Normally-off pGaN Transistors |
192 |
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8.6.2 Normally-on HEMT: Cascode Design |
195 |
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8.7 Conclusions |
201 |
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References |
201 |
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9 Performance-Limiting Traps in GaN-Based HEMTs: From Native Defects to Common Impurities |
204 |
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9.1 Surface-Related Trapping |
209 |
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9.2 Impact of Iron Doping |
212 |
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9.2.1 Properties of Deep Level E2 and Impact of Iron Doping |
212 |
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9.2.2 Origin of the Trap E2 |
215 |
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9.2.3 Impact of Electrical Stress on Trapping Mechanisms |
217 |
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9.3 Impact of Carbon Doping |
219 |
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9.4 Trapping Mechanisms in Metal Insulator Semiconductor High-Electron-Mobility Transistors (MIS-HEMTs) |
226 |
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9.4.1 Origin of the Trapping Induced by Positive Gate Bias |
227 |
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9.4.2 Analysis of Fast and Slow Trapping Mechanisms |
230 |
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9.4.3 Materials and Deposition Techniques for the Improvement of Trapping Effects |
230 |
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References |
234 |
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10 Cascode Gallium Nitride HEMTs on Silicon: Structure, Performance, Manufacturing, and Reliability |
244 |
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10.1 Motivation and Configuration of the Cascode GaN HEMT |
244 |
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10.2 Functionality and Benefits of Cascode GaN HEMT |
245 |
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10.3 Key Applications and Performance Advantage of Cascode GaN HEMTs |
246 |
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10.3.1 Diode-Free Half-Bridge Architecture |
246 |
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10.3.2 Gate-Drive Considerations |
247 |
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10.4 Products in the Market |
249 |
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10.5 Applications and Key Performance Benefits |
250 |
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10.5.1Totem-Pole Power Factor Correction Circuit (PFC) |
250 |
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10.5.2 PV Inverters |
251 |
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10.5.3 All-in-One Power Supplies with GaN AC–DC PFC and Full-Bridge Resonant Switching LLC DC–DC Con ... |
251 |
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10.6 Qualification and Reliability of Cascode GaN HEMTs |
253 |
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10.6.1 JEDEC Qualification |
254 |
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10.6.2 Extended Qualification/Reliability Testing |
255 |
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10.6.3 Operating and Intrinsic Lifetime Testing |
256 |
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10.7 Manufacturing Excellence |
258 |
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10.8 On Single-Chip e-Mode GaN |
259 |
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10.9 Future Outlook |
260 |
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10.9.1 Next-Generation Products |
260 |
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10.9.2 Intellectual Property Considerations |
260 |
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10.9.3 In Summary |
260 |
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Acknowledgments |
261 |
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References |
261 |
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11 Gate Injection Transistors: E-mode Operation and Conductivity Modulation |
262 |
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11.1Operation Principle of GIT |
262 |
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11.2DC and Switching Performances ofGIT |
263 |
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11.3 State-of-the-Art Reliability of GIT |
268 |
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11.4 Applications ofGIT to Practical Switching Systems |
270 |
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11.5 Advanced Technologies ofGIT for Future Power Electronics |
275 |
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11.6 Summary |
278 |
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Acknowledgments |
278 |
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References |
279 |
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12 Fluorine-Implanted Enhancement-Mode Transistors |
280 |
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12.1 Introduction: Fluorine in III-Nitride Heterostructures: Robust Vth Control |
280 |
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12.2 Physics Mechanism of Fluorine Implantation |
282 |
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12.2.1 Atomistic Modeling of F Plasma Ion Implantation |
282 |
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12.2.2 Stability of F Ions in AlGaN/GaN Heterostructures |
284 |
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12.2.3 Electron Binding Energy Around F Ions |
287 |
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12.3 Fluorine-Implanted Enhancement-Mode GaN MIS-HEMTs |
288 |
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12.3.1 GaN MIS-HEMTs |
288 |
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12.3.2 GaN MIS-HEMTs with Partially Recessed Fluorine-Implanted Barrier |
291 |
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12.3.3 GaN Smart Power ICs |
293 |
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12.4 Conclusions |
298 |
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Acknowledgments |
298 |
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References |
299 |
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13 Drift Effects in GaN High-Voltage Power Transistors |
301 |
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13.1 Introduction |
301 |
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13.2 Drift Effects and Their Physical Mechanisms |
302 |
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13.2.1 Overview |
302 |
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13.2.2 Basic Physical Understanding |
302 |
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13.2.3 Dependency on Device Operation Conditions |
305 |
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13.3 Drift Phenomena in GaN Power Switching Transistors |
306 |
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13.3.1 Dynamic On-State Resistance (Ron_dyn) |
306 |
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13.3.1.1 Power Switching from Off-State Bias Point |
307 |
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13.3.1.2 Trapping Effects During On-State Operation |
313 |
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13.3.2Threshold Voltage Shift |
313 |
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13.3.3Kink Effect |
314 |
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13.4 Technological Countermeasures |
316 |
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13.4.1 Optimized Epitaxial Buffer Design |
317 |
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13.4.2 Reduction of Electrical Field in Critical Device Regions |
318 |
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Acknowledgments |
320 |
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References |
320 |
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14 Reliability Aspects of 650-V-Rated GaN Power Devices |
324 |
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14.1 Introduction |
324 |
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14.2Reliability of Au-Free Ohmic Contacts |
324 |
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14.2.1 Introduction to Ohmic Contact Reliability |
324 |
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14.2.2 Au-Free Ohmic Contacts Processing |
325 |
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14.2.3 Stressing and Measurement Procedure |
326 |
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14.2.4Reliability Evaluation of Au-Free Ohmic Contacts |
328 |
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14.2.4.1 Degradation as a Function of Contact Spacing |
328 |
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14.2.4.2 Degradation as a Function of Stress Power |
328 |
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14.2.4.3 Temperature Dependence and Activation Energy |
330 |
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14.2.4.4 Failure Mechanisms |
332 |
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14.2.5 Conclusions |
334 |
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14.3 Intrinsic Reliability of MISHEMT Gate Dielectrics |
334 |
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14.3.1 Introduction |
334 |
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14.3.2 Experiments |
335 |
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14.3.3 Analysis of Leakage Current Under Forward Bias Condition |
336 |
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14.3.4 Analysis of Leakage Current Under Reverse Bias Condition |
339 |
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14.3.5 Analysis of Defect States in Bulk SiN |
340 |
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14.3.6 TDDB Study |
340 |
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14.3.7 Conclusions |
343 |
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14.4 Buffer Stack Reliability—Off-State High-Voltage Drain Stress |
343 |
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14.4.1 Introduction |
343 |
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14.4.2 Current Conduction Mechanism |
344 |
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14.4.3 High-Temperature Reverse Bias |
344 |
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14.4.4 High-Voltage off-State Drain Stress |
346 |
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14.4.5 Conclusions |
347 |
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References |
348 |
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15 Switching Characteristics of Gallium Nitride Transistors: System-Level Issues |
350 |
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15.1 Switching Characteristics of E-mode and Cascode GaN |
351 |
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15.1.1 Switching Loss Mechanism |
351 |
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15.1.2 Packaging Influence |
352 |
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15.1.3 Comparison Between Hard Switching and Soft Switching |
356 |
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15.2 Special Issues of Cascode GaN |
357 |
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15.2.1 Impact of Packaging on Gate Breakdown |
357 |
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15.2.2 Impact of Capacitor Mismatch |
358 |
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15.2.2.1 Si Avalanche |
358 |
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15.2.2.2 Failure to Achieve ZVS |
360 |
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15.2.2.3 Divergent Oscillation |
361 |
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15.2.2.4 Solution to Solve Capacitor Mismatch Issue |
363 |
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15.3 Gate Driver Design for GaN Device |
364 |
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15.3.1 The di/dt Issue |
364 |
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15.3.2 The dv/dt Issue |
365 |
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15.4 System-Level Impact |
368 |
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15.4.1 3D Integrated Point-of-Load Converter |
368 |
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15.4.2 Isolated DC/DC Converter |
371 |
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15.4.2.1 48–12 V DCX |
371 |
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15.4.2.2 400–12 V DCX |
372 |
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15.4.3 MHz Totem-Pole PFC Rectifier |
374 |
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15.4.4High-Density Wall Adapter |
377 |
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15.5 Summary |
378 |
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References |
379 |
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Author index |
381 |
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Subject index |
382 |
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